1. Technical Field
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device and a layout structure of a sub-word line control signal generator, capable of reducing power consumption and noise and improving an enable speed of the sub-word line by providing a relatively differential layout of the sub-word line control signal and a sub-word line control signal supply line.
2. Description
In general, as a DRAM (Dynamic Random Access Memory) becomes relatively highly integrated and larger in capacity, a time required to transfer a signal increases as compared with a delay time of a memory cell array itself due to a resistance problem of wire. As a result, a length of the wire needs to be appropriately divided to optimize a delay time. For example, a word line to select a row in the memory cell array is appropriately divided to optimize the delay time.
A word line is coupled to a gate terminal of an access transistor constituting a memory cell, and is generally formed of polysilicon. Specific resistance of polysilicon may be high. Moreover a capacitance may be high since the word line passes an upper part of gate oxide of a cell transistor. In other words, when a resistance of the word line becomes great, an RC delay increases and a decoder output terminal driving the word line should be large. Thus, an area size increases and much power is consumed in charging the entire word line to a high voltage, and then discharging it. Therefore, the length of the word line needs to be optimized to reduce resistance.
One approach to solve this problem has been to use a hierarchical divided word line structure to drive a sub-word line. The structure can include dividing a word line into sub-word lines of proper length and combining a main word line of a row decoder and sub-word lines of a sub-word line driver.
In the hierarchical word line structure, a word line is divided into proper lengths and is provided as sub-word lines SWL, and the sub-word lines SWL are driven by a row decoder and a sub-word line driver SWD. The row decoder may be classified as a main word line driver MWD and a sub-word line control signal generator (hereinafter, referred to as ‘PXI generator’).
The SWD is controlled by a main word line signal NWE output from the MWD and a sub-word line control signal PXI output from the PXI generator.
FIG. 1 illustrates a layout related to a word line selection in a semiconductor memory device according to a conventional art. As shown in FIG. 1, a plurality of memory blocks MBi, MBj and MBk are disposed in a horizontal second direction. Each of the memory blocks MBi, MBj and MBk comprise a plurality of sub-memory blocks SMB arrayed in a vertical first direction.
In a row decoder area, PXI generators PG13 and PG02 are configured to generate a sub-word line control signal PXI<0-3>. An MWD is configured adjacent to the PXI generators PG13 and PG02. Further, a sub-word line control driver (PXI driver) PD for amplifying sub-word line control signal PXI<0-3> generated in the PXI generators PG13 and PG02, and supplying the signal to the sub-word line driver SWD, is disposed on a conjunction area of a memory core region. The sub-word line control drivers PD use a high voltage of VPP level as a power source voltage, and drive output signals as a high voltage (VPP) level.
The SWD is disposed in an area between two sub-memory cell blocks SMB in a vertical direction. The SWD drives a sub-word line (not shown) in response to a main word line signal NWE generated in the MWD and output signals PXID of the sub-word line control driver PD.
The sub-word line control signal PXI and the output signals PXID of the sub-word line control driver PD have the same voltage level, and the output signals PXID of the sub-word line control driver PD are signals amplified from the sub-word line control signal PXI, thus all of them are commonly called herein a sub-word line control signal PXI.
Operation to drive a sub-word line is described as follows. A row address RA to select a desired sub-word line is applied. For example, when the row address RA is 14 bits, a portion RA13-2 of row address is input to the MWD, i.e., reference number 10, and the rest of the row address RA1-0 is input to the PXI generators PG13 and PG02. The main word line driver 10 generates a block selection signal BS into the PXI generators PG13 and PG02, to activate or select a PXI generator, i.e., reference numbers 12 and 14, corresponding to a specific memory block, i.e., MBj.
The PXI generators 12 and 14 generate the sub-word line control signal PXI into any one of plural, i.e., four, sub-word line control signal supply lines, in response to the row address RA1-0. For example, the PXI generator 12 generates a first sub-word line control signal PXI1. The first sub-word line control signal PXI1 is amplified by the sub-word line control driver 30 and supplied to a sub-word line driver 40. The sub-word line driver 40 enables one sub-word line in response to the first sub-word line control signal PXI1 and main word line signal NEW supplied through a main word line MWL from the main word line driver 10. The main word line signal NWE may have a row enable state. The enable state of the sub-word line may be accomplished by performing a switching operation to supply the first sub-word line control signal PXI1 to a selected sub-word line.
In a conventional semiconductor memory device having the structure described above, respective ones of sub-word line control drivers PD are alternately disposed every two sub-array memory blocks SMB. Further, output lines of the sub-word line control drivers PD, that is, supply lines of sub-word line control signals PXI<1,3> and PXI<0,2>, are disposed as a T-shape in horizontal and vertical directions. Thus, the line length of sub-word line control signals PXI<1,3> and PXI<0,2> is relatively long and a load thereof is relatively large. Thus, VPP power consumption through the sub-word line control drivers PD may be great, and a drive speed for the sub-word line may be relatively slow.
Furthermore, it is the structure that one sub-word line control signal PXI is supplied even to a non-selected memory block, i.e., MBi, thus a VPP power consumption is great. And, as the sub-word line control driver PD is disposed at a conjunction area of a memory core region, a plurality of VPP power lines to supply a VPP power source to the sub-word line control drivers PD must be used. The VPP power lines may be disposed overlapping in an upper part of memory block or disposed in a core region. The VPP power lines acts as a noise source in a semiconductor memory device, thus causing a noise disturbance.
Accordingly, some embodiments of the invention provide a semiconductor memory device and a layout structure of a PXI generator. Power consumption and noise can be reduced. In addition, an enable speed of a sub-word line can be improved. Furthermore, a VPP voltage consumption can decrease, while maintaining high integration.
According to an embodiment of the invention, a layout structure of sub-word line control signal (PXI) generator may be configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array may be characterized in that at least two sub-word line control signal generators are disposed, respectively, at edge areas of an area of the memory cell array, and configured to directly supply the sub-word line control signal to one selected sub-word line driver.
The sub-word line control signal may be directly supplied from the PXI generator to the sub-word line driver without a specific driver, amplifier, or repeater. The memory cell array may comprise a plurality of memory blocks, each memory block having an area including a plurality of sub-memory blocks arrayed in a first direction, the plurality of memory blocks being arrayed in a second direction intersected to the first direction, and wherein the sub-word line driver may be disposed at core regions between the sub-memory blocks.
A supply line of the sub-word line control signal may be disposed overlapping on one memory block area in the first direction, the first direction being a length-wise direction, to supply the sub-word line control signal to at least one sub-word line driver adapted within the one memory block area. The predefined voltage level may be a VPP voltage level higher than an array voltage supplied to the memory cell array.
The PXI generator may generate the sub-word line control signal in response to a given address signal. The sub-word line control signal supply line may be disposed so as to simultaneously supply the sub-word line control signal from the at least two sub-word line control signal generators to sub-word line drivers included in at least two memory blocks.
According to another embodiment of the invention, a semiconductor memory device comprises a plurality of memory blocks, each memory block having an area including a plurality of sub-memory blocks arrayed in a first direction, the plurality of memory blocks being arrayed in a second direction intersected to the first direction; a plurality of sub-word line control signal generators, of which at least two correspond to one sub-word line of a sub-memory block, and are disposed, respectively, at edge areas of a memory block, the plurality of sub-word line control signal generators configured to generate a sub-word line control signal; a plurality of sub-word line drivers configured to supply a signal having the same level as the sub-word line control signal to the one sub-word line, the plurality of sub-word line drivers being disposed in a core region between the sub-memory blocks; and control signal supply lines for directly supplying the sub-word line control signal to the plurality of sub-word line drivers without using a repeater, the sub-word line control signal being generated using the sub-word line control signal generators, the sub-word line control signal having a predefined voltage level.
Each of the PXI generators may have a structure to generate a sub-word line control signal of a predefined voltage level in response to a given address signal and to supply the sub-word line control signal to at least one sub-word line driver of one memory block selected without being supplied to other memory blocks.
Supply lines corresponding to one sub-word line control signal among the control signal supply lines may comprise a first supply line disposed in a first direction as a length direction and a second supply line disposed in a second direction as a width direction. The first supply line may be coupled between the at least two sub-word line control signal generators that are disposed at both edge areas of the memory block in the first direction, and the second supply line may be disposed to couple at least one corresponding sub-word line driver with the first supply line. The first supply line may be disposed overlapping on the memory block area.
The PXI generator may generate the sub-word line control signal in response to the given address and a block selection signal to select a memory block. The sub-word line control signal may be supplied to sub-array blocks adapted within at least two adjacent memory blocks.
According to another embodiment of the invention, a layout structure of PXI generator may be configured to supply a sub-word line control signal to a sub-word line driver to enable a sub-word line of a memory cell array may be characterized in that the PXI generator corresponds to one sub-word line driver, the sub-word line control signal generator being divided into a main generator and a sub-generator for simultaneously supplying the sub-word line control signal to one supply line, the main generator and the sub-generator being disposed, respectively, at edge areas of the memory cell array.
The main generator may be disposed at a row decoder area about an edge area of the memory cell array, and the sub-generator may be disposed at an area opposite to a layout area of the main generator. The memory cell array may comprise a plurality of memory blocks arrayed in a second direction intersected to a first direction, each memory block including a plurality of sub-memory blocks arrayed in the first direction, the sub-word line driver being disposed in core regions within an area of each memory block.
The supply line may be disposed overlapping the memory block in the first direction, the first direction being a length-wise direction.
According to some embodiment of the invention, power consumption can be reduced including that of VPP voltage, and the number of VPP power lines can be reduced, thereby decreasing noise. In addition, a memory core region can be utilized, thereby obtaining a high integration. Furthermore, a word line can be enabled without a speed decrease even without adapting a sub-word line control driver.